Data slicers are well known in the art. They can be one key element of a data transmission system. A data slicer receives an analog input signal and returns at its output a digital signal which is its estimate of the digital information sent during that baud period. A binary slicer accepts an analog input (usually described to be scaled between a minimum of −1 and a maximum of +1) and returns a digital binary output. The logical equivalent of a data slicer is to provide an output of −1 for input signals less than zero and an output of +1 for inputs greater than zero.
Multilevel data transmission systems quantize transmitted data into more than two levels, thereby using less channel bandwidth than the same capacity binary system. One such multilevel data transmission system is PAM-4, which encodes sequential pairs of binary data, such as, −1−1, −1+1, +1−1, and +1+1 into a four-level signal as for example, −3, −1, +1, and +3, respectively. The slicer at the PAM-4 receiver must reconstruct the transmitted signal by comparing the input to three different thresholds, −2, 0, and +2. Hence, if the input is less than −2, then the slicer output is −3. If the input is greater than −2 but less than zero, then the slicer output is −1. If the input is greater than zero but less than +2, the output is +1. If the input is greater than 2, then the output is +3.
Since transistors are inherently binary devices, and are most easily and reliable switchable between two states (on, off), PAM-4 slicers are usually physically realized using a combination of three binary slicers, with the reference input of each slicer tied, at least in concept, to −2, 0, and +2, respectively. The two binary data bits are then reconstructed using a simple logic circuit.
Practical implementations of PAM-4 slicers for a monolithic modern high speed communication system, especially one implemented in low voltage complementary metal oxide semiconductor (CMOS), is difficult. All of the high speed analog signals are run differentially. The problem therefore presents itself as to how to introduce the appropriate DC offsets into the signals provided to the +2 binary slicer and the −2 binary slicer. Still further, it is desirable to provide offset voltages for the upper and lower binary comparators which are symmetrical to assure that the thresholds of the upper and lower binary comparators are equally spaced from the threshold of the intermediate comparator. The present invention addresses this need.